SystemVerilog for Design & Verification

SystemVerilog

is far more than Verilog with a ++ operator. A hands-on knowledge of this rich language is critical for chip design and verification engineers. This thorough course starts from the synthesis-friendly RTL (register transfer level) parts of the language. You'll learn new syntax for describing digital logic and busing:  structures; enumeration; interfaces. The course then introduces OOP (object-oriented program) syntax, including classes, methods, and constrained random data—laying a solid foundation for UVM verification. As a final project, you can choose between:  a factorial-generator datapath design (RTL code); or a testbench to generate randomized Ethernet frames (OOP code).

Course Highlights:

Course Learning Outcomes:

• Write SystemVerilog code to describe practical digital logic functions, intuitively and concisely
• Rapidly debug your code, identifying and fixing syntax issues—whether common or obscure
• Confidently employ SystemVerilog code enhancements and conveniences such as:  ticked literals ('1) packed/unpacked arrays, imported packages, and user-defined type definitions (typedef)
• Utilize new syntax like typedef, struct, and enum to customize your code to application-specific
  chip architectures or data-packet formats. Add assert statements to check key design properties
• Develop reusable testbench code for simulating logic functions or bus operations, including defining a class of objects, calling its methods, constraining random stimuli, and using interface connections
• Explain the key pillars of OOP. Identify the SystemVerilog keywords or constructs that support object encapsulation, inheritance, and polymorphism. State how they enable UVM verification methodology

Course Typically Offered: Online in every quarter.

Prerequisite: Familiarity with digital logic and a working knowledge of any programming language.

Next Step: After completeting this course consider taking other courses in our Digital Signal Processing or Wireless Engineering certificate programs.

Contact: For more information about this course, please email unexengr@ucsd.edu.

Course Number: ECE-40301
Credit: 3.00 unit(s)
Related Certificate Programs: Digital Signal Processing, Embedded Systems Engineering, Wireless Engineering

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3/26/2024 - 5/25/2024

$845

Online

Closed

• SECTION ID:

  179739

• CLASS TYPE:

  Online Asynchronous.
  
  This course is entirely web-based and to be completed asynchronously between the published course start and end dates. Synchronous attendance is NOT required.
  You will have access to your online course on the published start date OR 1 business day after your enrollment is confirmed if you enroll on or after the published start date.

• INSTRUCTOR:
  

  Dančak, Charles

  Charles Dančak MSEE, MS Solid-State Physics, has worked as a trainer and consultant in Silicon Valley for many years. He spent ten years at Synopsys as a Staff Engineer, where he developed and taught hands-on workshops in ASIC and FPGA synthesis , verification, and testing. Earlier in his career, he was an MOS process engineer at an Intel Wafer Fab. As an instructor, Charles draws on his years of industry experience, providing students with real-world insights and illustrations. He developed the first course in SystemVerilog for UC Extension in Silicon Valley. Prior to that, he taught hands-on Verilog workshops at company sites including:  AMD, Broadcom, Freescale, Maxtor, nVIDIA, Qualcomm and TI. Mr. Dančak is knowledgeable in all aspects of CMOS chip d...Read More

• TEXTBOOKS:

  No textbook required.

• POLICIES:

  No refunds after: 4/1/2024.
  

• NOTE:

• DATE & LOCATION:

  3/26/2024 - 5/25/2024
  extensioncanvas.ucsd.edu
  You will have access to your course materials on the published start date OR 1 business day after your enrollment is confirmed if you enroll on or after the published start date.